| Part No. |
Description |
Pins |
| 00 | Quad 2-input NAND gates | 14 |
| 01 | Quad 2-input open-collector NAND gates | 14 |
| 02 | Quad 2-input NOR gates | 14 |
| 03 | Quad 2-input open-collector NAND gates | 14 |
| 04 | Hex inverters | 14 |
| 05 | Hex open-collector inverters | 14 |
| 06 | Hex open-collector high-voltage inverters. Maximum output voltage is 30V | 14 |
| 07 | Hex open-collector high-voltage buffers. Maximum output voltage is 30V. | 14 |
| 08 | Quad 2-input AND gates | 14 |
| 09 | Quad 2-input open-collector AND gates | 14 |
| 10 | Triple 3-input NAND gates | 14 |
| 11 | Triple 3-input AND gates. | 14 |
| 12 | Triple 3-input open-collector NAND gates | 14 |
| 13 | Dual 4-input NAND gates with schmitt-trigger inputs. | 14 |
| 14 | Hex inverters with schmitt-trigger inputs. | 14 |
| 15 | Triple 3-input open-collector AND gates | 14 |
| 16 | Hex open-collector high-voltage inverters. Maximum output voltage is 15V | 14 |
| 17 | Hex open-collector high-voltage buffers. Maximum output voltage is 15V | 14 |
| 18 | Dual 4-input NAND gates with schmitt-trigger inputs | 14 |
| 19 | Hex inverters with schmitt-trigger line-receiver inputs | 14 |
| 20 | Dual 4-input NAND gates | 14 |
| 21 | Dual 4-input AND gates | 14 |
| 22 | Dual 4-input open-collector NAND gates | 14 |
| 23 | Dual 4-input Expandable NOR w/strobe | 16 |
| 24 | Quad 2-input NAND gates with schmitt-trigger line-receiver inputs | 14 |
| 25 | Dual 4-input NOR gates with enable input | 14 |
| 26 | Quad 2-input open-collector high-voltage NAND gates. Maximum output voltage is 15V | 14 |
| 27 | Triple 3-input NOR gates | 14 |
| 28 | Quad 2-input NOR gates with buffered outputs | 14 |
| 29 | | 14 |
| 30 | 8-input NAND gate | 14 |
| 31 | Hex delay elements | 16 |
| 32 | Quad 2-input OR gates | 14 |
| 33 | Quad 2-input open-collector NOR gates | 14 |
| 34 | Hex Buffer | 14 |
| 35 | Hex Buffer open-collector | 14 |
| 36 | ---- | -- |
| 37 | Quad 2-input NAND gates with buffered output | 14 |
| 38 | Quad 2-input open-collector NAND gates with buffered output | 14 |
| 39 | Quad 2-input positive NAND buffers with open-collector outputs | 14 |
| 40 | Dual 4-input NAND gates with buffered output | 14 |
| 41 | ---- | -- |
| 42 | 1-of-10 inverting decoder/demultiplexer | 16 |
| 43 | 4-line to 10-line decoders (excess 3 to decimal) | 16 |
| 44 | 4-line to 10-line decoders (3-gray to decimal) | 16 |
| 45 | BCD to decimal decoder/driver | 16 |
| 46 | Open-collector BCD to 7-segment decoder/common-anode LED driver with ripple blank input and output. | 16 |
| 47 | Open-collector BCD to 7-segment decoder/common-anode LED driver with ripple blank input and output. | 16 |
| 48 | BCD to 7-segment decoders/drivers | 16 |
| 49 | BCD to 7-segment decoders/drivers (open-collector outputs) | 14 |
| 50 | Dual 2-wide 2-input AND-OR-INVERT gates (one gate expandable) | 14 |
| 51 | 2-wide 2-input and 2-wide 3-input AND-NOR gates | 14 |
| 52 | Expandable 4-wide AND-OR gates | 14 |
| 53 | Expandable 4-wide AND-OR-INVERT gates | 14 |
| 54 | 4-wide 2/3-input AND-NOR gate | 14 |
| 55 | 2-wide 4-input AND-NOR gate | 14 |
| 56 | 50-to-1 Frequency Divider | 8 |
| 57 | 60-to-1 Frequency Divider | 8 |
| 58 | 2-wide 2-input and 2-wide 3-input AND-OR gates | 14 |
| 59 | ---- | -- |
| 60 | Dual 4-input expanders | 14 |
| 61 | Triple 3-input expanders | 14 |
| 62 | 4-wide AND-OR expanders | 14 |
| 63 | Hex current-sensing interface gates | 14 |
| 64 | 4-2-3-2 input AND-OR-INVERT gates | 14 |
| 65 | 4-2-3-2 input AND-OR-INVERT gates | 14 |
| 66 | ---- | -- |
| 67 | ---- | -- |
| 68 | Dual 4-bit decade counter | 16 |
| 69 | Dual 4-bit binary counter | 14 |
| 70 | AND-Gated J-K positive edge triggered flip-flops | 14 |
| 71 | AND-OR-Gated J-K master-slave flip-flops with preset | 14 |
| 72 | J-K flip-flop with triple ANDed J an K inputs, set and reset | 14 |
| 73 | Dual positive-edge-triggered J-K flip-flop with reset | 14 |
| 74 | Dual D flip-flop with set and reset | 14 |
| 75 | Dual 2-bit transparent latches with complementary outputs | 16 |
| 76 | Dual J-K flip-flops with set and reset | 16 |
| 77 | 4-bit bistable latches | 14 |
| 78 | Dual negative-edge-triggered J-K flip-flops with common clock, set and common reset | 14 |
| 79 | ---- | -- |
| 80 | Gated full adders | 14 |
| 81 | 16-bit Random-Access-Memories | 14 |
| 82 | 2-bit binary full adder | 14 |
| 83 | 4-bit binary full adder with fast carry | 16 |
| 84 | 16-bit Random-Access-Memories | 16 |
| 85 | 4-bit noninverting magnitude comparator with cascade inputs | 16 |
| 86 | Quad 2-input XOR gates | 14 |
| 87 | 4-bit true/complement, zero/one elements | 14 |
| 88 | 256-bit read-only-memories | 16 |
| 89 | 64-bit read/write memories | 16 |
| 90 | 4-bit asynchronous decade counter with /2 and /5 sections, set(9) and reset | 14 |
| 91 | 8-bit serial-in serial-out shift register with two AND gated serial inputs and complementary outputs | 14 |
| 92 | 4-bit asynchronous divide-by-twelve counter with /2 and /6 sections and reset | 14 |
| 93 | 4-bit asynchronous binary counter with /2 and /8 sections and reset | 14 |
| 94 | 4-bit shift registers | 16 |
| 95 | 4-bit universal shift register with separate shift and parallel-load clocks | 14 |
| 96 | 5-bit shift register with asynchronous reset and asynchronous preset inputs | 16 |
| 97 | 6-bit synchronous binary rate multiplier | 16 |
| 98 | 4-bit data selector/storage registers | 16 |
| 99 | 4-bit bidirectional universal shift registers | 16 |
| 100 | 8-bit bistable latches | 24 |
| 101 | AND-OR-Gated J-K negative edge triggered flip-flops with preset | 14 |
| 102 | AND-Gated J-K negative edge triggered flip-flops with preset and clear | 14 |
| 103 | Dual J-K negative edge triggered flip-flops with clear | 14 |
| 104 | ---- | -- |
| 105 | ---- | -- |
| 106 | Dual J-K negative edge triggered flip-flops with preset and clear | 16 |
| 107 | Dual J-K flip-flops with clear | 14 |
| 108 | Dual J-K negative edge triggered flip-flops with preset, common clear and common clock | 14 |
| 109 | Dual J-/K positive edge triggered flip-flops with preset and clear | 14 |
| 110 | AND-Gated J-K master-slave flip-flops with data lockout | 14 |
| 111 | Dual J-K master-slave flip-flops with data lockout | 16 |
| 112 | Dual J-K negative edge triggered flip-flops with preset and clear | 16 |
| 113 | Dual J-K negative edge triggered flip-flops with preset | 14 |
| 114 | Dual J-K negative edge triggered flip-flops with preset, common-clear and common-clock | 14 |
| 115 | ---- | -- |
| 116 | Dual 4-bit latches | 24 |
| 117 | ---- | -- |
| 118 | ---- | -- |
| 119 | ---- | -- |
| 120 | Dual pulse synchronizers/drivers | 16 |
| 121 | Monostable multivibrators | 14 |
| 122 | Retriggerable monostable multivibrators with clear | 14 |
| 123 | Dual retriggerable monostable multivibrators with positive and negative inputs and direct clear | 16 |
| 124 | Dual voltage-controlled oscillators with enable inputs | 16 |
| 125 | Quad bus buffer gates with three-state outputs | 14 |
| 126 | Quad bus buffer gates with three-state outputs | 14 |
| 127 | ---- | -- |
| 128 | Line Drivers | 14 |
| 129 | ---- | -- |
| 130 | ---- | -- |
| 131 | 3 to 8 line decoder/demultiplexer with address registers | 16 |
| 132 | Quad 2-Input positive NAND schmitt triggers | 14 |
| 133 | 13-Input positive NAND | 16 |
| 134 | 12-Input positive NAND gates with three-state outputs | 16 |
| 135 | Quad exclusive OR/NOR gates | 16 |
| 136 | Quad exclusive OR gates with open-collector outputs | 14 |
| 137 | 3 to 8 line decoders/demultiplexers with address latches | 16 |
| 138 | 3 to 8 line decoders/demultiplexers | 16 |
| 139 | Dual 2 to 4 line decoders/demultiplexers | 16 |
| 140 | Dual 4-input positive NAND 50-ohm line drivers | 14 |
| 141 | BCD to decimal decoder/driver | 16 |
| 142 | Counter/latch/decoder/driver | 16 |
| 143 | Counters/latchs/decoders/drivers | 24 |
| 144 | Counters/latchs/decoders/drivers | 24 |
| 145 | BCD to decimal decoders/drivers for lamps, relays, MOS | 16 |
| 146 | ---- | -- |
| 147 | 10-Line decimal to 4-line BCD priority encoders | 16 |
| 148 | 8 to 3 line octal priority encoders | 16 |
| 149 | ---- | -- |
| 150 | 1 of 16 data selectors/multiplexers | 24 |
| 151 | 1 of 8 data selectors/multiplexers | 16 |
| 152 | 1 of 8 data selectors/multiplexers | 14 |
| 153 | Dual 4-line to 1-line data selectors/multiplexers | 16 |
| 154 | 4-line to 16-line decoders/demultiplexers | 24 |
| 155 | Decoders/Demultiplexers | 16 |
| 156 | Decoders/Demultiplexers | 16 |
| 157 | Quad 2 to 1 line data selectors/multiplexers | 16 |
| 158 | Quad 2 to 1 line data selectors/multiplexers | 16 |
| 159 | 4 to 16 line decoders/demultiplexers | 24 |
| 160 | Synchronous 4-bit counters (decade, direct clear) | 16 |
| 161 | Synchronous 4-bit counters (binary, direct clear) | 16 |
| 162 | Synchronous 4-bit counters (decade, synchronous clear) | 16 |
| 163 | Synchronous 4-bit counters (binary, synchronous clear) | 16 |
| 164 | 8-Bit parallel out serial shift registers (synchronous clear) | 14 |
| 165 | 8-Bit shift register (parallel load with complementary outputs) | 16 |
| 166 | 8-Bit shift register (parallel/serial input, serial output) | 16 |
| 167 | Synchronous decade rate multipliers | 16 |
| 168 | 4-Bit up/down synchronous counters (decade) | 16 |
| 169 | 4-Bit up/down synchronous counters (binary) | 16 |
| 170 | 4-by-4 register files | 16 |
| 171 | Quad d-type flip-flops with clear | 16 |
| 172 | 16-Bit register files | 24 |
| 173 | 4-Bit d-type registers (3-state outputs) | 16 |
| 174 | Hex d-type flip-flops (single-rail ouputs, common direct clear) | 16 |
| 175 | Quad d-type flip-flops (complementary outputs, common direct clear) | 16 |
| 176 | Presettable decade/biquinary counters | 14 |
| 177 | Presettable binary counters | 14 |
| 178 | 4-Bit universal shift register | 14 |
| 179 | 4-Bit universal shift registers | 16 |
| 180 | 9-Bit odd/even parity generator/checker | 14 |
| 181 | Arithmetic logic units/function generators (16 arithmetic operations,16 logic functions) | 24 |
| 182 | Look-ahead carry generators | 16 |
| 183 | Dual carry-save full adders | 14 |
| 184 | Code converters (BCD to binary) | 16 |
| 185 | Code converters (Binary to BCD) | 16 |
| 186 | ---- | -- |
| 187 | 1024-bit read-only-memories (256 4-bit words, open-collector outputs) | 16 |
| 188 | 256-bit programmable read-only-memories | ?? |
| 189 | 64-Bit ramdom-access-memories (16 4-bit words, 3 state outputs) | 16 |
| 190 | Synchronous up/down counters (BCD) | 16 |
| 191 | Synchronous up/down counters (Binary) | 16 |
| 192 | Synchronous up/down dual clock counters (BCD with clear) | 16 |
| 193 | Synchronous up/down dual clock counters (Binary with clear) | 16 |
| 194 | 4-Bit bidirectional universal shift registers | 16 |
| 195 | 4-Bit parallel-access shift registers | 16 |
| 196 | Presettable decade/biquinary counters/latches | 14 |
| 197 | Presettable binary counters/latches | 14 |
| 198 | 8-bit bidirectional universal shift registers | 24 |
| 199 | 8-bit bidirectional universal shift registers (J-/K serial inputs) | 24 |
| 200 | ---- | -- |
| 201 | 256-Bit random-access-memories (256 1-bit words, 3 state outputs) | 16 |
| 202 | ---- | -- |
| 203 | ---- | -- |
| 204 | ---- | -- |
| 205 | ---- | -- |
| 206 | ---- | -- |
| 207 | ---- | -- |
| 208 | ---- | -- |
| 209 | ---- | -- |
| 210 | ---- | -- |
| 211 | ---- | -- |
| 212 | ---- | -- |
| 213 | ---- | -- |
| 214 | ---- | -- |
| 215 | ---- | -- |
| 216 | ---- | -- |
| 217 | 256-Bit random-access-memories with three state outputs (64 x 4-bit words) | 20 |
| 218 | 256-Bit random-access read/write memories with three state outputs (32 x 8-bit words) | 20 |
| 219 | 64-Bit random-access-memories (16 x 4-bit words) | 16 |
| 220 | ---- | -- |
| 221 | Dual monostable multivibrators | 16 |
| 222 | 64-Bit FIFO memories 16 4-bit words (input-ready enable, output-ready enable, 3-state output) | 20 |
| 223 | ---- | -- |
| 224 | 64-Bit FIFO memories 16 4-bit words (3 state output) | 16 |
| 225 | 80-Bit FIFO memories 16 5-bit words | 20 |
| 226 | 4-Bit parallel latched bus transceivers (3 state outputs) | 16 |
| 227 | 64-Bit FIFO memories 16 4-bit words (input-ready enable, output-ready enable, open-collector outputs) | 20 |
| 228 | 64-Bit FIFO memories 16 4-bit words (open-collector outputs) | 16 |
| 229 | ---- | -- |
| 230 | Octal buffers and line drivers (3 state output) | 20 |
| 231 | Octal buffers and line drivers (3 state output) | 20 |
| 232 | ---- | -- |
| 233 | ---- | -- |
| 234 | ---- | -- |
| 235 | ---- | -- |
| 236 | ---- | -- |
| 237 | ---- | -- |
| 238 | ---- | -- |
| 239 | ---- | -- |
| 240 | Octal buffers/Line drivers/Line receivers (inverted 3 state outputs) | 20 |
| 241 | Octal buffers/Line drivers/Line receivers (non-inverted 3 state outputs) | 20 |
| 242 | Quad bus tranceivers (inverted 3 state outputs) | 14 |
| 243 | Quad bus tranceivers (non-inverted 3 state outputs) | 14 |
| 244 | Octal buffers/Line drivers/Line receivers (non-inverted 3 state outputs) | 20 |
| 245 | Octal bus tranceivers (non-inverted 3 state outputs) | 20 |
| 246 | BCD to seven segment decoders/drivers with ripple blanking | 16 |
| 247 | BCD to seven segment decoders/drivers with ripple blanking | 16 |
| 248 | BCD to seven segment decoders/drivers (internal pull-up outputs) | 16 |
| 249 | BCD to seven segment decoders/drivers (open-collector outputs) | 16 |
| 250 | ---- | -- |
| 251 | Data selectors/multiplexers (true and inverted 3 state outputs) | 16 |
| 252 | ---- | -- |
| 253 | Dual data selectors/multiplexers (3 state outputs) | 16 |
| 254 | ---- | -- |
| 255 | ---- | -- |
| 256 | ---- | -- |
| 257 | Quad data selectors/multiplexers (non-inverted 3 state outputs) | 16 |
| 258 | Quad data selectors/multiplexers (inverted 3 state outputs) | 16 |
| 259 | 8-Bit addressable latches | 16 |
| 260 | Dual 5-input positive NOR gates | 14 |
| 261 | 2-Bit by 4-bit parallel binary multipliers | 16 |
| 262 | ---- | -- |
| 263 | ---- | -- |
| 264 | ---- | -- |
| 265 | Quad complementary output elements | 16 |
| 266 | Quad 2-input exclusive NOR gates with open-collector outputs | 14 |
| 267 | ---- | -- |
| 268 | ---- | -- |
| 269 | ---- | -- |
| 270 | 2048-Bit read-only-memories (open-collector outputs, 512 x 4-bit words) | 16 |
| 271 | 2048-Bit read-only-memories (open-collector outputs, 256 x 8-bit words) | 20 |
| 272 | ---- | -- |
| 273 | Octal d-type flip-flops (common clock, single rail outputs) | 20 |
| 274 | 4-Bit by 4-bit binary multipliers | 20 |
| 275 | 7-Bit slice wallace trees | 16 |
| 276 | Quad J-/K flip-flops (seperate clocks, edge-triggering, common direct clear and preset) | 20 |
| 277 | ---- | -- |
| 278 | 4-bit cascadable priority registers | 14 |
| 279 | Quad /S./R latches | 16 |
| 280 | 9-Bit odd/even parity generators/checkers | 14 |
| 281 | 4-Bit parallel binary accumulators | 24 |
| 282 | ---- | -- |
| 283 | 4-Bit binary full adders | 16 |
| 284 | 4-Bit by 4-bit parallel binary multipliers used with '285 | 16 |
| 285 | 4-Bit by 4-bit parallel binary multipliers used with '284 | 16 |
| 286 | ---- | -- |
| 287 | ---- | -- |
| 288 | ---- | -- |
| 289 | 64-Bit random-acces-memories (16 x 4-bit words, open collector outputs) | 16 |
| 290 | Decade counters (divide-by-two and divide-by-five) | 14 |
| 291 | ---- | -- |
| 292 | Programmable frequency dividers/digital timers (digitally programmable from 2^2 to 2^31) | 16 |
| 293 | 4-Bit binary counters (divide-by-two and divide-by-eight) | 14 |
| 294 | Programmable frequency dividers/digital timers (digitally programmable from 2^2 to 2^15) | 16 |
| 295 | 4-Bit bidirectional universal shift registers | 14 |
| 296 | ---- | -- |
| 297 | Digital phase-locked-loop filters (cascadable for higher-order loops) | 16 |
| 298 | Quad 2-input multiplexers with storage | 16 |
| 299 | 8-Bit bidirectional universal shift/storage registers (3 state outputs) | 20 |
| 300 | ---- | -- |
| 301 | 256-Bit random-access-memories (256 1-bit words, open collector outputs) | 16 |
| 302 | ---- | -- |
| 303 | ---- | -- |
| 304 | ---- | -- |
| 305 | ---- | -- |
| 306 | ---- | -- |
| 307 | ---- | -- |
| 308 | ---- | -- |
| 309 | ---- | -- |
| 310 | ---- | -- |
| 311 | ---- | -- |
| 312 | ---- | -- |
| 313 | ---- | -- |
| 314 | ---- | -- |
| 315 | ---- | -- |
| 316 | ---- | -- |
| 317 | 256-Bit random-access-memories with open-collector outputs (64 x 4-bit words) | 20 |
| 318 | 256-Bit random-access-memories with open-collector outputs (32 x 8-bit words) | 20 |
| 319 | 64-Bit random-access-memories (16 x 4-bit words, open-collector outputs) | 16 |
| 320 | Crystal controlled oscillators | 16 |
| 321 | Crystal controlled oscillators (with F/2 and F/4 count-down outputs) | 16 |
| 322 | 8-Bit shift registers with sign extend (3-state outputs, multiplexed I/O) | 20 |
| 323 | 8-Bit bidirectional shift/storage registers (3 state outputs) | 20 |
| 324 | Voltage Controlled Oscillator | 14 |
| 325 | ---- | -- |
| 326 | ---- | -- |
| 327 | ---- | -- |
| 328 | ---- | -- |
| 329 | ---- | -- |
| 330 | ---- | -- |
| 331 | ---- | -- |
| 332 | ---- | -- |
| 333 | ---- | -- |
| 334 | ---- | -- |
| 335 | ---- | -- |
| 336 | ---- | -- |
| 337 | ---- | -- |
| 338 | ---- | -- |
| 339 | ---- | -- |
| 340 | ---- | -- |
| 341 | ---- | -- |
| 342 | ---- | -- |
| 343 | ---- | -- |
| 344 | ---- | -- |
| 345 | ---- | -- |
| 346 | ---- | -- |
| 347 | BCD to seven-segment decoders/drivers (open-collector outputs, low voltage version of 'LS47) | 16 |
| 348 | 8-Line to 3-line priority encoders (3 state outputs) | 16 |
| 349 | ---- | -- |
| 350 | ---- | -- |
| 351 | Dual 8-line to 1-line data selectors/multiplexers (3 state outputs, four common data inputs) | 20 |
| 352 | Dual 4-line to 1-line data selectors/multiplexers (inverting version of 'LS153) | 16 |
| 353 | Dual 4-line to 1-line data selectors/multiplexers (3 state outputs,inverting version of 'LS253) | 16 |
| 354 | 8-line to 1-line data selectors/multiplexers/transparent registers (3 state outputs) | 20 |
| 355 | 8-Line to 1-line data selectors/multiplexers/transparent registers (open-collector outputs) | 20 |
| 356 | 8-Line to 1-line data selectors/multiplexers/edge-triggered registers (3 state outputs) | 20 |
| 357 | 8-Line to 1-line data selectors/multiplexers/edge-triggered registers (open-collector outputs) | 20 |
| 358 | ---- | -- |
| 359 | ---- | -- |
| 360 | ---- | -- |
| 361 | ---- | -- |
| 362 | ---- | -- |
| 363 | ---- | -- |
| 364 | ---- | -- |
| 365 | Hex bus drivers (non-inverted 3-state outputs, gated enable inputs) | 16 |
| 366 | Hex bus drivers (inverted 3-state outputs, gated enable inputs) | 16 |
| 367 | Hex bus drivers (non-inverted 3-state outputs organised to facilitate handling of 4-bit data) | 16 |
| 368 | Hex bus drivers (inverted 3-state outputs organised to facilitate handling of 4-bit data) | 16 |
| 369 | ---- | -- |
| 370 | 2048-Bit read-only-memories (512 x 4-bit words, 3-state outputs) | 16 |
| 371 | 2048-Bit read-only-memories (256 x 8-bit words, 3-state outputs) | 20 |
| 372 | ---- | -- |
| 373 | Octal d-type latches (3-state outputs, common output control, common enable) | 20 |
| 374 | Octal d-type flip-flops (3-state outputs, common output control, common clock) | 20 |
| 375 | 4-Bit bistable latches | 16 |
| 376 | Quad J-/K flip-flops (common clock, common clear) | 16 |
| 377 | Octal d-type flip-flops (single rail outputs, common enable, common clock) | 20 |
| 378 | Hex d-type flip-flops (single rail outputs, common enable, common clock) | 16 |
| 379 | Quad d-type flip-flops (single rail outputs, common enable, common clock) | 16 |
| 380 | ---- | -- |
| 381 | Arithmetic logic units/function generators (8 binary functions, use 'S182 for look-ahead carry) | 20 |
| 382 | Arithmetic logic units/function generators (ripple carry and overflow outputs) | 20 |
| 383 | ---- | -- |
| 384 | 8-Bit by 1-bit two's-complement multipliers | 16 |
| 385 | Quad serial adders/subtractors | 20 |
| 386 | Quad 2-input exclusive-OR gates | 14 |
| 387 | ---- | -- |
| 388 | ---- | -- |
| 389 | ---- | -- |
| 390 | Dual decade counters (bi-quinary or bcd sequences) | 16 |
| 391 | ---- | -- |
| 392 | ---- | -- |
| 393 | Dual 4-bit binary counters | 14 |
| 394 | ---- | -- |
| 395 | 4-Bit universal shift registers (3-state outputs) | 16 |
| 396 | Octal storage registers (parallel access) | 16 |
| 397 | ---- | -- |
| 398 | Quad 2-input multiplexers with storage (double-rail outputs) | 20 |
| 399 | Quad 2-input multiplexers with storage | 16 |
| 400 | ---- | -- |
| 401 | ---- | -- |
| 402 | ---- | -- |
| 403 | ---- | -- |
| 404 | ---- | -- |
| 405 | ---- | -- |
| 406 | ---- | -- |
| 407 | ---- | -- |
| 408 | ---- | -- |
| 409 | ---- | -- |
| 410 | ---- | -- |
| 411 | ---- | -- |
| 412 | Multi-mode buffered 8-bit latches (3-state outputs, direct clear) | 24 |
| 413 | ---- | -- |
| 414 | ---- | -- |
| 415 | ---- | -- |
| 416 | ---- | -- |
| 417 | ---- | -- |
| 418 | ---- | -- |
| 419 | ---- | -- |
| 420 | ---- | -- |
| 421 | ---- | -- |
| 422 | Re-triggerable monostable multivibrators (internal timing resistor) | 14 |
| 423 | Re-triggerable monostable multivibrators | 16 |
| 424 | ---- | -- |
| 425 | Quad gates (3-state outputs, active-low enabling) | 14 |
| 426 | Quad gates (3-state outputs, active-high enabling) | 14 |
| 427 | ---- | -- |
| 428 | System controller for 8080A | 28 |
| 429 | ---- | -- |
| 430 | ---- | -- |
| 431 | ---- | -- |
| 432 | ---- | -- |
| 433 | ---- | -- |
| 434 | ---- | -- |
| 435 | ---- | -- |
| 436 | Line driver/memory driver circuits - MOS memory interface | 16 |
| 437 | Line driver/memory driver circuits - MOS memory interface | 16 |
| 438 | System controller for 8080A | 28 |
| 439 | ---- | -- |
| 440 | Quad tridirectional bus transceivers (open-collector outputs, non-inverted logic) | 20 |
| 441 | Quad tridirectional bus transceivers (open-collector outputs, inverted logic) | 20 |
| 442 | Quad tridirectional bus transceivers (3-state outputs, non-inverted logic) | 20 |
| 443 | Quad tridirectional bus transceivers (3-state outputs, inverted logic) | 20 |
| 444 | Quad tridirectional bus transceivers (3-state outputs, inverted and non-inverted logic) | 20 |
| 445 | BCD-to-decimal decoders/drivers | 16 |
| 446 | Quad bus tranceivers with direction controls (3-state outputs) | 16 |
| 447 | BCD-to-seven-segment decoders/drivers (low-voltage version of 'LS247) | 16 |
| 448 | Quad tridirectional bus transceivers (open-collector outputs, inverted and non-inverted logic) | 20 |
| 449 | Quad bus tranceivers with direction controls (3-state outputs) | 16 |
| 450 | ---- | -- |
| 451 | ---- | -- |
| 452 | ---- | -- |
| 453 | ---- | -- |
| 454 | ---- | -- |
| 455 | ---- | -- |
| 456 | ---- | -- |
| 457 | ---- | -- |
| 458 | ---- | -- |
| 459 | ---- | -- |
| 460 | ---- | -- |
| 461 | ---- | -- |
| 462 | ---- | -- |
| 463 | ---- | -- |
| 464 | ---- | -- |
| 465 | Octal buffers with 3-state outputs (true outputs) | 20 |
| 466 | Octal buffers with 3-state outputs (inverted outputs) | 20 |
| 467 | Octal buffers with 3-state outputs (true outputs) | 20 |
| 468 | Octal buffers with 3-state outputs (inverted outputs) | 20 |
| 469 | ---- | -- |
| 470 | ---- | -- |
| 471 | ---- | -- |
| 472 | ---- | -- |
| 473 | ---- | -- |
| 474 | ---- | -- |
| 475 | ---- | -- |
| 476 | ---- | -- |
| 477 | ---- | -- |
| 478 | ---- | -- |
| 479 | ---- | -- |
| 480 | ---- | -- |
| 481 | 4-Bit slice cascadable processor elements | 48 |
| 482 | 4-Bit slice cascadable control elements | 20 |
| 483 | ---- | -- |
| 484 | BCD-to-binary code converter | 20 |
| 485 | Binary-to-BCD code converter | 20 |
| 486 | ---- | -- |
| 487 | ---- | -- |
| 488 | ---- | -- |
| 489 | ---- | -- |
| 490 | Dual decade counters | 16 |
| 491 | ---- | -- |
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| 518 | 8-Bit magnitude comparator (input pull-up resistor, open-collector output) | 20 |
| 519 | 8-Bit magnitude comparator (open-collector output) | 20 |
| 520 | 8-Bit magnitude comparator (input pull-up resistor, inverted totem-pole output) | 20 |
| 521 | 8-Bit magnitude comparator (inverted totem-pole output) | 20 |
| 522 | 8-Bit magnitude comparator (input pull-up resistor, inverted open-collector output) | 20 |
| 523 | ---- | -- |
| 524 | ---- | -- |
| 525 | ---- | -- |
| 526 | ---- | -- |
| 527 | ---- | -- |
| 528 | ---- | -- |
| 529 | ---- | -- |
| 530 | ---- | -- |
| 531 | ---- | -- |
| 532 | ---- | -- |
| 533 | Octal d-type transparent latches (3-state buffer-type outputs) | 20 |
| 534 | Octal d-type edge-triggered flip-flops (3-state buffer-type outputs) | 20 |
| 535 | ---- | -- |
| 536 | ---- | -- |
| 537 | ---- | -- |
| 538 | 3 to 8 line decoders/demultiplexers (3-state outputs, output parity control) | 20 |
| 539 | 2 to 4 line decoders/demultiplexers (3-state outputs, output parity control) | 20 |
| 540 | Octal buffers and line drivers (inverted data output) | 20 |
| 541 | Octal buffers and line drivers (tru data output) | 20 |
| 542 | ---- | -- |
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| 556 | ---- | -- |
| 557 | ---- | -- |
| 558 | ---- | -- |
| 559 | ---- | -- |
| 560 | Synchronous 4-bit counters (decade, sync and async clear) | 20 |
| 561 | Synchronous 4-bit counters (binary, sync and async clear) | 20 |
| 562 | ---- | -- |
| 563 | Octal d-type transparent latches (inverted outputs) | 20 |
| 564 | Octal d-type edge-triggered flip-flops (inverted outputs) | 20 |
| 565 | ---- | -- |
| 566 | ---- | -- |
| 567 | ---- | -- |
| 568 | Synchronous 4-bit up/down counters (decade, sync and async clear) | 20 |
| 569 | Synchronous 4-bit up/down counters (binary, sync and async clear) | 20 |
| 570 | ---- | -- |
| 571 | ---- | -- |
| 572 | ---- | -- |
| 573 | Octal d-type transparent latches (functionally equivalent to 'LS373 & 'S373) | 20 |
| 574 | Octal d-type edge-triggered flip-flops (functionally equivalent to 'LS374 & 'S374) | 20 |
| 575 | Octal d-type edge-triggered flip-flops (non-inverted outputs) | 24 |
| 576 | Octal d-type edge-triggered flip-flops (inverted outputs) | 20 |
| 577 | Octal d-type edge-triggered flip-flops (inverted outputs, synchronous clear) | 24 |
| 578 | ---- | -- |
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